Computer Organization MCQ SET-9

Computer organization and Architecture MCQ with Questions and Answers


1. The addressing mode where you directly specify the operand value is





Answer : (A) Immediate


2. How is the effective address of base-register calculated?





Answer : (A) By addition of base register contenns to the partial address in instruction


3. The associative access mechanism is followed in





Answer : (D) both (a) and (b)


4. The users view of memory is supported by





Answer : (A) paging


5. The largest delay in accessing data on disk is due to





Answer : (A) seek time


Computer Organization MCQ

6. Address of memory location for fetching data needs to be deposited in memory in





Answer : (A) MAR


7. if k be the number of registers and n be the size of each register then in order
to constract n-line common bus system using tri-state buffers the total number of
tri-state buffers and the size of decoder would be





Answer : (B) n*k and log2 k to k


8. RAM is called DRAM(Dynamic RAM) when





Answer : (A) it is requires periodic refreshing


9. In order to execute a program instructions must be transferred from
memory along a bus to the cpu. if the bus has 8 data lines at most one 8 bit byte
can be transferred at a time How many memory accesses would br needed in this case to
transfer a 32 bit instruction from memory to the CPU?





Answer : (D) 4


10. A computer’s memory is composed of 8K words of 32 bits each How many bits are
are required for memory address if the smallest addressable memory unit is a word?





Answer : (C) 13


Computer Organization MCQ

11. Cache memory refers to





Answer : (B) fast memory present on the processor chip that is used to store rcently accessed data


12. Write Through technique is used in which memory for updating the data?





Answer : (D) Cache memory


13. ……… is generally used to increase the apparent size of physical memory.





Answer : (A) Virtual memory


14. The time delay between two successive initiations of memory operation is





Answer : (B) Memory cycle time


15. A 24 bit address generates an address space of ……. locations





Answer : (D) 16,777,216


Computer Organization MCQ

16. To get the physical address from the logical address generated by CPU we use





Answer : (C) MMU


17. During the transfer of data between the processor and memory we use





Answer : (D) Registers


18. The return address of the Sub-routine is pointed to by





Answer : (A) PC


19. The Instruction, Add R1,45 does





Answer : (B) Adds 45 to the value of R1 and stores it in R1


20. What could be the maximum size of on chip cache memory for an n-address bit processor?





Answer : (C) Infinite


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